Cornelis and NextSilicon announced on June 22nd at ISC High Performance 2026 a collaboration to build and evaluate joint reference architectures for AI and high-performance computing. The work pairs the Cornelis CN5000 fabric with the NextSilicon Maverick-2 compute platform. Joint evaluation is already underway, with the goal of commercialisation through joint OEM partners.
The collaboration starts with the 400 Gbps CN5000 fabric, launched in 2025, paired with Maverick-2, which began shipping in volume late that year. The first phase validates how fabric and compute perform together across configurations, so OEM partners start from proven combinations rather than untested parts lists. The companies plan to extend testing to the 800 Gbps CN6000 fabric, due in the second half of 2026.
Two Bottlenecks, One Design
Each company targets a different bottleneck. Standard Ethernet was not built for the small, latency-sensitive messages that AI inference and HPC simulation generate at scale. Congestion builds, and expensive compute sits idle waiting on data. The CN5000 is designed to eliminate that idle time.
On the compute side, the von Neumann model, which has defined processors for decades, shuttles data between memory and a fixed execution unit. It stalls on the irregular, data-dependent workloads that now dominate AI and HPC. NextSilicon built Maverick-2 on its Intelligent Compute Architecture (ICA), a software-defined dataflow design that reconfigures to each workload at runtime and runs existing code without modification.
Pairing the two addresses both limits at once: a fabric that keeps data moving and an accelerator that keeps compute busy. The joint reference architectures will give OEM partners a blueprint for systems they can build and bring to market.
“Operators keep telling us their most expensive systems sit idle, waiting on the network,” said Lisa Spelman, CEO of Cornelis. “We built the CN5000 to end that wait. NextSilicon challenges the same kind of assumption on the compute side, so this collaboration is a natural fit. Together we can show partners and customers what a congestion-free fabric and a workload-driven compute architecture deliver as one design.”
“For decades, software had to bend to fit the processor,” said Elad Raz, founder and CEO of NextSilicon. “Maverick-2 makes the processor adapt to the software. Cornelis takes the same approach to the network. Evaluating our architectures together is the first step toward giving customers and OEM partners a faster, more efficient foundation for AI and HPC.”
Looking Ahead: Disaggregated Inference
Along with HPC, the collaboration will also target the shift in AI inference toward Mixture of Experts (MoE) models and agentic AI. Production inference for these workloads no longer runs as one model on one accelerator. Inference splits into stages, and data moves between stages across the network.
This pattern, often called disaggregated inference, makes the fabric part of the compute path. It rewards a network that moves small, bursty, latency-sensitive messages without congestion and compute that adapts to each stage of the pipeline. As the CN6000 reaches availability in the second half of 2026, the companies intend to evaluate how a congestion-free fabric and a reconfigurable compute architecture can support disaggregated and agentic inference, with findings intended to inform future OEM reference designs.
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